In conventional semiconductor circuit layout, dimensions and spacing of features can be specified along Cartesian, or X-Y axes. Reducing, or scaling down (hereinafter “scaling”) the dimensions and spacing has long been an objective, for purposes including compressing more functionality into a smaller volume, and increasing operating speed. Conventional geometric techniques for scaling semiconductor circuits can apply a generally symmetric scaling, i.e., the same scaling factor along the X and the Y axes. This can provide an area reduction of approximately the square of the scaling factor. However, costs of such scaling both X and Y can be substantial. For example as we migrate to multi patterning territory of design rules.